SRAM Static Random Access Memory Chip 32MB 1.7V 2V 8-bit TFBGA W958D8NBYA5I-TR
• Interface: HyperBus
• Power supply: 1.7V~2.0V
• Maximum clock rate: 250MHz
• Double-Data Rate (DDR) Up to 500 MB/s
• Clock: – Single ended clock (CK) – Differential clock (CK/CK#)
• Chip Select (CS#)
• 8-bit data bus (DQ[7:0])
• Hardware reset (RESET#)
• Read-Write Data Strobe (RWDS) – Bidirectional Data Strobe / Mask – Output at the start of all transactions to indicate
refresh latency – Output during read transactions as Read Data
Strobe – Input during write transactions as Write Data
Mask
Performance and Power
• Configurable output drive strength
• Power Saving Modes – Hybrid Sleep Mode – Deep Power Down
• Operating temperature range: -40°C ≤ TCASE ≤ 85°C
• Configurable Burst Characteristics – Linear burst – Wrapped burst lengths: – 16 bytes (8 clocks) – 32 bytes (16 clocks) – 64 bytes (32 clocks) – 128 bytes (64 clocks) – Hybrid burst - one wrapped burst followed by
linear burst
• Array Refresh Modes – Full Array Refresh – Partial Array Refresh
• Support package:
24 balls TFBGA
HyperBus is a low signal count, Double Data Rate (DDR) interface, that achieves high speed read and write throughput.
The DDR protocol transfers two data bytes per clock cycle on the DQ input/output signals. A read or write transaction
on HyperBus consists of a series of 16-bit wide, one clock cycle data transfers at the internal HyperRAM array with two
corresponding 8-bit wide, one-half-clock-cycle data transfers on the DQ signals. All inputs and outputs are LV-CMOS
compatible.
Command, address, and data information is transferred over the eight HyperBus DQ[7:0] signals. The clock (CK#, CK)
is used for information capture by a HyperBus slave device when receiving command, address, or data on the DQ
signals. Command or Address values are center aligned with clock transitions.
Every transaction begins with the assertion of CS# and Command-Address (CA) signals, followed by the start of clock
transitions to transfer six CA bytes, followed by initial access latency and either read or write data transfers, until CS# is
de-asserted.
Read and write transactions require two clock cycles to define the target row address and burst type, then an initial
access latency of tACC. During the CA part of a transaction, the memory will indicate whether an additional latency for
a required refresh time (tRFH) is added to the initial latency; by driving the RWDS signal to the High state. During the
CA period the third clock cycle will specify the target word address within the target row. During a read (or write)
transaction, after the initial data value has been output (or input), additional data can be read from (or written to) the row
on subsequent clock cycles in either a wrapped or linear sequence. When configured in linear burst mode, the device
will automatically fetch the next sequential row from the memory array to support a continuous linear burst.
Simultaneously accessing the next row in the array while the read or write data transfer is in progress, allows for a linear
sequential burst operation that can provide a sustained data rate of 500 MB/s (1 byte (8 bit data bus) * 2 (data clock
edges) * 250 MHz = 500 MB/s).
Packaging and transportation instructions
- According to the standard export packaging.
Customers can choose from cartons, wooden cases and wooden pallets according to their own requirements.
Q&A
1. How to obtain the price?
We usually quote within 24 hours after receiving your inquiry (except weekends and holidays). If you are in urgent need of a price, please send us an email or contact us in any other way so that we can provide you with a quotation.
2. What is your delivery time?
This depends on the quantity of the order and the season in which you place the order. Usually, we can ship the goods within 7 to 15 days (for small batches), and for large batches, it takes about 30 days.
3. What are your payment terms?
Factory price, 30% deposit, 70%T/T payment before shipment.
4. What is the mode of transportation?
It can be transported by sea, air or express delivery (EMS, UPS, DHL, TNT, FEDEX, etc.). Please confirm with us before placing an order.
5. How do you help our business establish a long-term and good relationship?
We maintain good quality and competitive prices to ensure that our customers benefit.
2. We respect every customer as our friend. We do business with them sincerely and make friends with them, no matter where they come from.
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32MB 1.7V 2V PSRAM Chip 8 Bit TFBGA W958D8NBYA5I-TR Static Random Access Memory Chip Images
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